The present invention relates to the field of programmable integrated circuits and in particular, to a techniques and circuitry for more rapidly configuring programmable integrated circuits.
Integrated circuits are important building blocks of the modern age. Technology continues to evolve and integrated circuits continue to provide improved functionality. As integrated circuits improve, so do the electronics systems that are built using integrated circuits. There are many types of integrated circuit such as memories, microprocessors, application specific integrated circuits (ASICs), and programmable logic. Programmable logic integrated circuits such as PALs, PLDs, FPGAs, LCAs, and others are becoming more complex and continually evolving to provide more user-programmable features on a single integrated circuit. Modern programmable logic integrated circuits incorporate programmable logic including logic gates, products terms, or look-up tables. Programmable logic integrated circuits also included embedded user-programmable memory or RAM.
Despite the success of programmable logic, there is a continuing desire to provide greater functionality in a programmable logic integrated circuit, but at the same time, provide greater performance. As programmable logic becomes more highly integrated, more logical functions are provided, and therefore, more configuration bits are required to program or configure the functionality. More configuration bits leads to longer configuration or programming times, which is undesirable. For example, this may cause relatively long system start-up times because programmable logic having volatile memory cells such as static RAM cells need to be reprogrammed upon power up.
Therefore, there is a need to provide techniques and circuitry for more rapidly configuration programmable integrated circuit.
The invention provides techniques and circuitry for more rapidly configuring programmable integrated circuits. Configuration data is input into a programmable integrated circuit in parallel, and this data is also handled internally in parallel. The configuration data will be stored in a data register. This data register is segmented or divided into two or more segments, each segment being made up of a serial chain of registers. The configuration data is input into the two of more segments of the data registers in parallel. Circuitry is also provided to handle redundancy.
In an embodiment, the invention is a programmable logic integrated circuit. The integrated circuit has n configuration bit inputs to input in parallel, n bits at a time, k configuration bits. The variable n is an integer greater than 1, k is greater than n, and k is a number of configuration bits in a frame for configuring the programmable logic of the programmable logic integrated circuit. The integrated circuit also has a data register to store at least the k configuration bits. The data register is divided into n segments and each of n configuration bits inputs is connected to input configuration bits at one of n segmentation nodes. In a specific embodiment, n is 8. The registers may be implemented or interchanged with latches, flip-flops, or other circuitry to implement the equivalent functionality.
Furthermore, the programmable logic integrated circuit may include a cyclic redundancy check (CRC) circuit, which is connected to a first the n configuration bit inputs. The cyclic redundancy check circuit performs a cyclic redundancy check on the configuration bits transferred through the first of the n configuration bit inputs. The circuitry will generate an error signal in the case of an error.
The programmable logic integrated circuit may also include a first multiplexer having a first input connected to a second configuration bit input of the n configuration bit inputs, a second input connected to a last register of a first segment of the data register, and a first multiplexer output connected to a first register of a second segment of the data register. The first register of the second segment is used to hold configuration data for a row L of the logic array blocks. A second multiplexer has a first input connected to the second configuration bit input of the n configuration bit inputs, a second input connected to a last register to hold configuration data for row L of the logic array block, and a second multiplexer output connected to a first register to hold configuration data for a row L+1 of the logic array blocks. When row L of logic array blocks is determined to be defective, data at the second configuration bit input of the n configuration bit inputs is output using the second multiplexer to the first register for row L+1 of the logic array blocks.
In a further embodiment, the invention is a method of configuring a programmable logic integrated circuit. A number of configuration bits are input into the programmable logic integrated circuit in parallel using a first input and a second input. The configuration bits provided by the first input are loaded starting at a first register of a first segment a data register. The first segment includes registers connected together in a serial chain. The configuration bits provided by the second input are loaded starting at a first register of a second segment the data register. The second segment also includes registers connected together in a serial chain
In another embodiment, the invention is a programmable integrated circuit including a first data input and a second data input. A data register to hold configuration bits used to configure the programmable integrated circuit. The data register includes a first segment with a number of registers connected in a serial chain and a second segment with a number of registers connected in a serial chain. The first register of the first segment is connected to the first data input. A first multiplexer is connected to the second data input, a last register of the first segment, and a first register of the second segment. The first segment may have a different number of registers from the second segment. A number of static RAM cells may be configured using the configuration bits.
Furthermore, the first register of the second segment is for configuring a row L of the programmable integrated circuit. A second multiplexer is connected to the second data input, a register in the second segment which is a last register for row L, and a first register for a row L+1.